Integrated circuits (ICs) include external pins that allow the ICs to be connected to other external circuit elements. Although these external pins are required as a practical matter so ICs can be included in electronic products, unfortunately these external pins also make semiconductor devices on the ICs susceptible to potentially damaging electrostatic discharge (ESD) pulses. An ESD pulse, which is a sudden and unexpected voltage and/or current discharge, can transfer energy to devices on the IC through the external pins from an outside body (e.g., a human body, which can be approximated in modeling by a human body model (HBM)). ESD pulses can also affect internal nodes of the IC, as well as discrete devices that are not associated with ICs. In any case, an ESD pulse can damage electronic devices, for example by “blowing out” a gate oxide of a transistor in cases of high voltage or by “melting” an active region area of a device in cases of high current, causing junction failure. If devices are damaged by an ESD pulse, the electronic product can be rendered less operable than desired, or can even be rendered inoperable altogether.
To protect devices from ESD pulses, engineers have developed ESD protection devices. FIG. 1 shows an example of an integrated circuit 100 that includes one or more semiconductor devices 102 (e.g., transistors arranged as part of an application specific integrated circuit (ASIC)), which are coupled to an exterior circuit assembly via an external pin 104. The external pin 104 can be a supply pin that supplies a DC supply voltage (e.g., VDD or VSS) to the devices 102, or can be an input/output (I/O) pin that transfers input or output signals therefrom, for example. A conventional ESD protection device 106 is coupled between the semiconductor device(s) 102 and the external pin 104 to mitigate damage due to ESD pulses 108.
As shown in FIG. 2, if an ESD pulse 108 occurs (e.g., starting at time 110), the ESD protection device 106 detects the ESD pulse 108 and shunts the power associated with it away from the semiconductor device(s) 102 (e.g., as shown by arrow PESD), thereby preventing damage to the semiconductor device(s) 102. In addition to this shunting, which occurs during actual ESD events, this functionality can also be falsely triggered, for example, by supply switching noise, fast power up sequences having rise times comparable to ESD events, and other non-ESD events.
Although this conventional ESD protection functionality is well understood, the inventors have appreciated a shortcoming in that conventional ESD protection devices, when active, can undesirably reduce the desired voltage level of the signal expected to be delivered from the external pin 104 to the device(s) 102. For example, FIG. 2 shows an example where the external pin 104 is a supply pin that is expected to provide a DC voltage supply (VDD) of approximately 3.3 volts to the semiconductor device(s) 102. However, upon a 100 volt ESD pulse triggering the ESD protection device 106, the supply voltage that actually reaches the semiconductor device(s) 102 is reduced to about 1.5 V during the ESD pulse. See line 112. Because 1.5 V is less than the expected VDD and may be less than required to operate the semiconductor device(s) 102 (e.g., transistors in an ASIC), this can cause instability in the integrated circuit 100 and systems associated therewith. Other sample ESD pulses are also illustrated in FIG. 2, along with their corresponding effect on VDD delivered to the devices on the IC.
The applicants note that FIG. 2 is a simulation result in which transmission line pulsing (TLP) is used to approximate an ESD event. In FIG. 2's simulation, a constant current is delivered to a convention ESD protection device over a 100 ns period. Thus, at the start of the ESD pulse, an artificial voltage overshoot is exhibited, which is due to “slow” transistors. In real ESD events, the current actually delivered often tends to be transient and not as constant as shown by the simulation results of FIG. 2.
In view of the above, the inventors have devised ESD protection techniques that provide adequate ESD protection while still ensuring that substantially the same voltage as expected to be delivered to device(s) via an external pin (or other circuit node) is, in fact, delivered to the device(s) via the external pin (or other circuit node).